1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, more particularly to a flash memory which can select a source terminal and flash-erase memory data.
2. Description of the Related Art
The flash memory is a nonvolatile semiconductor memory, which can electrically write and erase data, and comprises an EEPROM (Electrically Erasable Programmable Read Only Memory). Particularly, the flash memory can flash-erase data by a predetermined unit. In the conventional flash memory, data stored in all memory cells of the chip was flash-erased (chip erase). However, in accordance with the large capacities of the memory, it has been required that data be rewritten by a small unit. Due to this, in recent years, the chip is divided into several blocks, and data can be block-erased by each block unit.
Also, in accordance with the advance in the large capacities of the flash memory, an electrical disk has been replaced by the flash memory. Then, it has been desired that the data writing unit be arranged to be a sector size of the electrical disk. Due to this, it is needed that data erasing be performed by the unit of 512 B (B: Byte), which is called as a sector erase. There is a tendency that the erase unit of the flash memory is made smaller in order of the chip erase, block erase, and sector erase. Particularly, in the flash memory of the large capacity, data erase by the sector unit is important.
The following will explain the cell data writing and erasing in the flash memory. The data writing and erasing is that a threshold voltage of a cell transistor is changed.
FIG. 9 shows a flash memory cell, which is mainly used at present. The memory cell has the same structure as an EPROM (Erasable Programmable Read Only Memory: PROM of ultraviolet ray erasing type) having a double gate structure. In this type of the memory cell, the data writing is exactly the same as EPROM. In other words, a source terminal S is grounded, and high voltage for writing is applied to a control gate CG and a drain D. Then, a hot electron generated close to the drain D is implanted to a floating gate, and the threshold voltage of the cell transistor is increased.
The following will explain two typical methods for erasing data. The first method is a source erase method (hereinafter called as SE). According to this method, as shown in FIG. 10A, the control gate CG is grounded, the drain D is opened, and high voltage VE for erasing (&gt;0) is applied to the source S. Then, a high electrical field is applied between the source and floating gate FG, and a tunnel current is generated. Thereby, an electron in the floating gate is drawn to the source S.
The second method is a source gate erase method (hereinafter called as SGE). According to this method, as shown in FIG. 10B, the drain D is in the same state as FIG. 10A. The source S is biased to VE1 (&gt;0), and the control gate CG is biased to a negative voltage VE2 (&lt;0). In the SEG method, the electrical field between the source and the floating gate, which is necessary for generation of a tunnel phenomenon, is generated by biasing the control gate to the negative voltage. Due to this, the SEG method has an advantage that the voltage to be applied to the source can be reduced as compared with the method shown in FIG. 10A. Therefore, in the SGE method, it is needed that the negative bias is supplied to the control gate, that is, the word line. However, in the SGE method, there can be overcome a problem in that a high break down voltage of the source is lowered in accordance with miniaturization. Moreover, it can be said that the SGE method is superior to the SE method in the point that the erase voltage is made lower, thereby making it easy to provide a single power source. In both methods, data is erased by drawing the electron from the floating gate, and reducing a threshold voltage of the cell transistor.
The following will explain the structure of the memory cell array, which is actually provided on the chip. A large number of word lines and a large number of bit lines are arranged to be perpendicular to each other in the memory cell array. FIG. 11 shows a part of the structure which is enlarged. The drains D are connected to the bit line BL, which is formed of an aluminum wire, through a contact hole CH every two cells adjacent in a vertical direction shown in the figure. The sources S are connected to each other every two cells adjacent in a vertical direction shown in the figure. Moreover, the sources of the memory cell (not shown) adjacent in a horizontal direction are connected to each other by a diffusion layer. The control gate CG is connected to the memory cell (not shown) adjacent in the horizontal direction, thereby forming a word line WL. The sources are provided in a portion, which is between two word lines WL and which is perpendicular to these word lines.
Here, the division of the memory array will be considered as follows:
The main cause that the division of the memory cell array is needed is the delay of access time. In the case that the number of cells per bit line and the number of cells per word line are increased, a parasitic capacity of the cell and a parasitic resistance of the cell largely delay the signal. Due to this, in consideration of the influence on access time, the memory cell array is divided as required.
Next, the division of the memory cell array in accordance with the erase unit will be considered as follows:
As mentioned above, in the case of the chip erase, since all cells are flash-erased, there is no need that the source and control gate (word line) are divided. However, in the case of the block erase, it is needed that the source be divided every erase block in the SE method. Also, it is needed that the source and word line be divided every erase block in the SGE method. According to the SE and SEG method, in each divided block, the erase voltage is applied to the memory cell through the commonly connected source. In the case of the SGE method, in order that the word lines can be individually controlled every block, it is required that a row decoder is provided in each block. However, the number of divisions of the word lines is normally determined to be linked with the division, which is performed in accordance with access time though the number of divisions differs depending on the capacity of the chip and the size of the erase block. Due to this, the number of divisions of the word lines is controlled to the extent that no problem occurs if the chip area is increased in erasing the blocks.
In contrast, in the case of the sector erase, since the erase is small, i.e., 512 B, one sector is generally formed of a several numbers of word lines. As shown in FIG. 11, the source is shared by two cells adjacent in the vertical direction. Due to this, in both cases of SE and SGE, two rows sharing the source are erased at the same time, and the sector is normally formed of at least two row units. In this case, so as to realize the sector size of 512 B, if the number of memory cells to be connected to one word line is 2 Kb, two row units are set, and if the number of memory cells is 1 Kb, four row units are set. In other words, an equation of 2 Kb.times.2=1 Kb.times.4=512 B is established.
Moreover, if the following process is provided, the sector can be divided into one row unit, and the number of memory cells per word line may be 4 Kb. More specifically, in the case of the SE method, in the two rows sharing the source, one word line is grounded, and set to be in an erasing state, and the other word line is biased to an intermediate such that the electric field between the floating gate and the source is relaxed and no erasing occurs. In this case, all memory cells to be connected to the word lines, which are biased to the intermediate voltage, must be set to satisfy two conditions, that is, data of the memory cell in a writing state is not erased, and data is not written in the memory cell, which is originally set in an erasing state. Therefore, suitable intermediate voltage, which satisfies the above two conditions, is needed.
FIG. 12 shows the division of the word lines in accordance with the sectors, that is, the division of the sectors. In the case of the sector division, the source lines SL (diffusion layer) are provided in the same direction as the word lines WL provided in the memory cell array MCA. It is needed that the erase voltage be applied to the source lines every sector. Due to this, as shown in FIG. 12, a source decoder SD is required so as to select the source in accordance with the address selected by the row decoder RD. The source decoder SD has a function of selecting the source in accordance with the row address, and level-converting the selected signal to a high voltage for erasing. In the SE and SGE methods, since a current flows into the source at the time of erasing because of the tunnel current between bands, current driving source is required in the transistor constituting the source decoder SD, and the transistor having a sufficient size must be ensured.
The following will explain the sector erase, whose importance is considered to be further increased in accordance with the large capacities of the memory. As mentioned above, in the case of the sector erase, the number of memory cells per one word line is limited by the sector size. In the example of FIG. 12, the number of memory cells per one word line is 2 Kb, and the sector size of 512 B can be obtained. If the number of memory cells per one bit line is set to 2 Kb, the capacity of the chip is 4 Mb and no division of the word lines can be realized. The flash memory, which is manufactured at present, has such a degree of the capacity. However, the flash memory having a capacity of 16 Mb or 64 Mb has already developed, and it is expected that the large capacity of the flash memory is further advanced. If the number of the memory cells per one word line is further increased in accordance with the large capacities of the memory, the word line division is indispensable for controlling the number of memory cells per one word line to 2 Kb. Moreover, high speed of access time has been strongly required in addition to the large capacity of the memory. The delay of the word line largely influences access time. In order to control the delay of the word line, it is needed that the number of memory cells per word line be reduced. Also, it is required that the word lines be divided in view of the high speed access. For these reasons, it is essential that the word lines be divided into a plurality of blocks, and that the source lines be not only decoded by the row address but also be selectively controlled every block.
As mentioned above, in the case of the sector erase, not only the row decoder RD but also complex structured source decoder SD is required every block. Due to this, in the case that the word lines are simply divided, the number of row decoders RD and that of source decoders SD are increased in proportion to the number of divisions. Therefore, there occurs a problem in which the chip size is enlarged as the number of the source decoders is increased, so that the manufacturing cost rises. Moreover, in the case of the memory having the large capacity, there are limitations such as size of an exposing area of the manufacturing device and a package size in enlarging the chip size.